Present invention relates generally to pre-charging circuitry and more specifically to a current compensating pre-charge circuit.
Bus lines in memory and other logic circuitry are generally pre-charged to a given value. As illustrated in FIG. 1, a logic 10 including a plurality of parallel devices Q1 through QN is connected between a bus line 11 and a first supply voltage illustrated as ground. A first logic level signal voltage at V1 through VN to any of the transistors Q1 through QN will activate the transistors and pull the bus 11 to the first supply voltage. The pre-charge circuitry 12 includes a pull-up device 14 illustrated as transistor P1 which is activated by a pre-charge signal PC to pull up the bus 11 to a second supply voltage Vcc. A latch 16 includes a transistor P2 and an inverter G1 which is responsive to the pre-charge signal on the bus 11 to activate and latch the transistor P2 on, maintaining the bus at the pre-charge value after expiration of the pre-charge signal. Upon actuation of any of logic gates Q1 through QN, the bus 11 is pulled to the first supply voltage and latch 12 is deactivated turning P2 off. The pull-up transistor Pl is typically sized to charge the bus to the second supply voltage source Vcc rapidly, whereas P2 is sized so as to maintain bus 11 above the switching threshold of inverter G1 when all logic gates Q1 through QN are deactivated. Also, any logic gate Q1 through QN, when activated, will pull the bus 11 below the switching threshold of the inverter G1. Pre-charge generally occurs when all parallel logic devices are deactivated by a second logic level signal voltage at V1 through VN to all transistors Q1 through QN.
Under process, temperature, or radiation effects, it may be difficult to establish a large enough size of P2 such that the bus 11 is held above the threshold of inverter G1 when the input devices Q1 through QN are off, and at the same time the size of P2 is small enough that Q1 through QN can individually pull bus 11 below the threshold of value G1 when they are on. For a complete discussion of the effect of currents of logic devices see Young U.S. Pat. No. 4,6613,772. Also typical example of a pre-charge circuitry with latch is illustrated Young U.S. Pat. No. 4,581,548.
Thus it is an object of the present invention to provide a pre-charge circuit which tracks parametric changes in logic devices connected to a common bus.
Another object of the present invention is to provide a more appropriately sized and responsive latch as part of the pre-charge circuit.
A still further object of the present invention is to provide a pre-charge circuit including a latch which compensates for process, temperature and radiation effects.
These and other objects are attained by providing a tracking circuit as a part of a latch in a pre-charge circuit maintaining a fixed deactivation voltage level of the latch. The tracking circuit includes an on-tracking circuit connected to the latch for tracking the characteristics of one of the input devices of the logic circuit being activated and an off-tracking circuit connecting to the latch for tracking the characteristics of all the input elements of the logic circuit being deactivated. The latch includes a pull-up transistor connected to the bus and a deactivation element, which is generally an inverter, connected to the bus for sensing the voltage on the bus and generating a latch deactivation signal when the deactivation voltage level of the deactivation device is exceeded.
The tracking circuit includes a first current mirror having the latch pull-up device as a drive device of the controlled leg and a controlling leg having a drive device interconnected to the second pull-up device. A first load of the controlling leg functioning as the on-tracking device being deactivated by the deactivation signal and having a current capacity of a predetermined ratio to a current capacity of one of the input devices being activated. The off tracking element may be a second load connected in parallel to the first load in the controlling leg of the first current mirror. It is also deactivated by said deactivation signal and has a current capacity of said predetermined ratio to the sum of the current capacity of all input devices being a deactivated. Alternatively, the off-tracking device may be a second current mirror having a controlled leg also connected to the bus. The off-tracking load includes a switch element which is responsive to the deactivation signal in series with a load having the appropriate current characteristics and biased in the same voltage which is used to turn off one of the input devices for the logic gate. A switch is provided for each of the current mirrors connecting the interconnection of the drive devices to the deactivation signal for disabling the current mirrors in response to the deactivation signal.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings